Four logic signals.
- SCLK — Serial Clock (output from master)
- MOSI/SIMO — Master Output, Slave Input (output from master)
- MISO/SOMI — Master Input, Slave Output (output from slave)
- SS — Slave Select (active low; output from master)
Data transimission:
During each SPI clock cycle, a full duplex data transmission occurs:
- the master sends a bit on the MOSI line; the slave reads it from that same line
- the slave sends a bit on the MISO line; the master reads it from that same line
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